Direction sensing and displacement detection apparatus



1957 T. 1'. KUMAGAI 2,808,650

DIRECTION SENSING AND DISPLACEMENT DETECTION APPARATUS Filed Aug. 16, 1956 2 Sheets-Sheet 2 t. yta 4 hsi'n i I02 I F Tom T. Kumogui,

INVENTOR.

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atent ()filice 2,808,650 Patented Oct. 8, 1957 assassa DIRECTION SENSING Alli DEELACEMENT DETECTION APPARATUS Tom T. Kumagai, Los Angeles, Calitl, ass guor to Hughes Aircraft Company, Culver City, Calif., u corporation of Delaware Application August 16, 1956, Serial No. 664,466

6 Claims. (Cl. 33-125) This invention relates to direct sensing and detection apparatus and more particularly to an apparatus responsive to periodic samples of the signals from two or more heads reading a linear scale, said apparatus being capable of sensing direction of movement along the scale and accurately determining the. extent of the movement.

The device of the present invention is operative in response to binary signals derived from a plurality of reading heads adapted to read a linear scale. These reading heads are grouped along the scale within a distance, M1, equal to one-mil periodicity or one-half wavelength." The individual reading heads are spaced at intervals equal to A/ZN along the scale, where N is the total number of reading heads. "ihe operation of the device is divided into two phases of operation designated as the serial shift" ant accumulator phases. Just prior to the commencement of the serial shift phase, means including a storage-shifting register is provided to sample and store the binary signals from the N heads. For the purpose of explanation, the newly sampled signals are referred to as the "present" configuration and the samples from the prior position are referred to as the last" configuration. In this respect, the maximum speed at which the heads traverse the scale must be limited to the extent that the present configuration of signals is never more than (N-l) positions away from the last configuration. A position is defined as the region throughout which the configuration of signals therefrom remains unchanged.

In addition to the above, the present device comprises an accumulator and apparatus [or storing the last configuration of signals which apparatus may be provided by time-sharing a circulating register or drum. In accordance with the invention, during the serial shift phase of operation, means is provided to serially shift the present and last configurations of signals out of their respective storage devices and compare corresponding bits to determine the number of disagreements or counts. A pulse corresponding to each of these counts is impressed on a counting device in order to determine the total number of counts or disagreements for each present and last configuration. 'llic total humour of counts represents the number of positions that the position corresponding to the present Configuration is away from that corresponding to the last configuration.

It now remains to be determined whether to add or subtract this number of positions from the sum already in the accumulator. In accordance with the invention, a selected bit of the new configuration is employed as a control bit to determine whether to subtract a particular bit of the last configuration from its corresponding bit of the present configuration or vice versa, i. e., to subtract the corresponding bit of the present configuration from the particular bit of the last configuration. It is generally preferred to use the bit of the present configuration which would be the last to be serially shifted from the storage shifting register so as to avoid the use of an additional flip-flop as will be hereinafter explained. rurtner, it may be necessary to alter the control bit in a predetermined manner when there is a particular type of correspondence between any two bits being compared. This altering of the control bit is chosen so that one or more carries generated from the afore-mentioned subtractions indicate a movement in the opposite direction. Hence, the curries thus generated may be employed to determine whether to add or subtract the number of counts from the sum in the accumulator whereby the resulting sum is changed by the net movement of the reading heads along the linear scale. This addition or subtraction is accomplished during the accumulator phase of operation.

It is therefore an object of the present invention to provide an improved direction sensing and detection apparatus which requires a minimum of equipment and logic gating elements.

Another object of the present invention is to provide a. direction sensing and detection apparatus responsive to signals from two or more reading heads thereby to provide a greater resolution of a given scale and permit the use of coarser scales.

Still another object of the present invention is to provide a direction sensing and detection apparatus capable of operating in response to signals from an increased number of reading heads without increasing the complexity of the logical gating.

A further object of the present invention is to provide a direction sensing and detection apparatus capable of operating in response to signals from more than two reading heads thereby enabling greater distances to be traversed between samplings whereby the maximum traverse speed along the controlled axis is increased.

The above-mentioned and other features and objects of this invention and the manner of attaining them will become more apparent by reference to the following description taken in conjunction with the accompanying drawings, wherein:

Fig. l is a schematic block diagram of a preferred embodiment of the device of the present invention; and

Fig. 2 illustrates several explanatory waveshapes at points throughout the device of Fig. 1.

Referring now to Fig. 1, there is shown a schematic block diagram of a preferred embodiment of the device of the present invention, which device is adapted to operate in response to binary signals derived from a plurality of reading heads. For the purposes of explanation, a device adapted to operate in conjunction with four reading heads is described. It is, however, clearly evident that any number of reading heads may be employed with only minor modifications. Further, although the present device, as shown, is adapted to operate in conjunction with magnetic reading heads, it is evident that optical or other equivalent systems may also be employed without departing from the spirit and scope of the invention.

Referring to the drawings, Fig. 1 shows a crosssectional view of a portion of a magnetic scale 10 together with an associated movable magnetic element 12. Magnetic scale 10 includes a series of transverse lands, such as lands 13, 14 and 15 with intervening grooves, all of which are of equal width. Magnetic element 12 is adapted to slide along the lands and includes a recess 16 located on the side thereof immediately adjacent the magnetic scale 10 for housing the four reading heads 17, 18, 19 and 20. When four reading heads are employed, as in the present case, they are disposed at successive intervals equal to cycle of the scale apart, N being the total number of reading heads. The width of one land and one groove is considered as one ccmplete cycle along the magnetic scale 10. With regard to the reading heads 17-20, each compriszs a magnetic core which is magnetically connectcd to the magnetic element 12 within the recess 16, each of which are tapered to a point in a direction transverse to the length of magnetic scale and are of a leng h such that the points substantially touch the lands as the magnetic element 12 slides along the scale 10. About the magnetic cores of the reading heads 172[l there are disposed coils 21, 22, 23 and 24, respectively. Because of the length that the magnetic element 12 extends along the magnetic scale 10, there is a very low reluctance path therebetween. Consequently, when the agnetic core of a particular reading head is over a land of the scale 10, the associated coil is threaded by a low reluctance path and, consequently, is more inductive than when the magnetic core is over a groove inasmuch as the air gap increases the reluctance of the path threading the coil, The terminals of the coils 21-24 of the reading heads 17-20 are coupled to binary signal generators 26, 27, 28, 29, respectively. The generators 26, 27, 28 and 29 are designed to derive a binary signal in accordance with the variations in inductance of the coils 21, 22, 23 and 24 in the manner disclosed in a copending application Serial No. 595,256, entitled Bridge Circuit for P0- sition Measuring Device, filed July 2, 1956, by William T. Chater. The aforementioned co-pending application and the present application are assigned to a common assignee. Thus, the binary signals produced by the binary signal generators 26 29 are indicative of whether the magnetic core of a particular reading head is over a land or a groove. In accordance with convention, the binary signal produced when a particular reading head is over a land is designated as being at the one" level and the signal produced in response to a reading head being over a groove is designated as being at the zero level. Employing this convention, the binary signals derived from the reading heads 17-20 by the binary signal generators 2629, respectively, for successive positions a, I], c, d, c, f, g, h, 1' (position of reading heads in drawing), j, k, 1, m, n, 0. p and q are tabulated in Table I as follows:

TABLE I In describing the apparatus of the present invention, a convention is employed wherein individual "and and or" gates are shown as semicircular blocks with the inputs applied to the straight side and the output appearing on the semicircular side. An and gate is indicated by a dot and an or gate by a plus in the semicircular block. As is generally known, an and gate produces a one" or information level output signal only when every input is at the information level whereas an "or" gate produces an information level output signal when any one of the input signals thereto are at the information level.

Also, in addition to the above, a convention is employed in describing the particular embodiment of the present invention wherein the upper and lower inputs to the flip-flops, as they appear in the drawing, are designated as the set and reset inputs, respectively. An information level signal applied to either the set or reset inputs of a flip-[lop will change its state in a manner such that an information level signal appears at the corresponding prir al er complementary output terminals, respectively. lur if information lcvel signals are applied to both the nd re et inputs of a flip-flop, the state of the flip-flop wilt change in accordance with the last signal applied.

Referring to Fig. l, the basic apparatus of the present invention comprises a storage shifting register 30 which includes storage fiip-llops Q1, Q2, Q3 and Q4; a circu ating istcr 32 which may be of the drum type and which includes a write flip-flop, Qw, and a read fiipdlop, Qr; a three-stage counting device 34 which includes ilip ops Cl and C2: and a full adder-subtractor 36 which may he of the type disclosed in Patent No. 2.,tlbl, ill. c lrd llrithmctic Units for Digital Computers issued to Ehlrerl C. Nelson on August 20, 957. The present t'levicc further includes a bit" counter 38, a phase-control flip-flop. Qp, a direction-sensing flip-flop, Cd, and gating matrices 4t) and 42.

The described apparatus is operated in a manner to time share the circulating register 3-2. In this respect, the circulating register 32 is adapted to store binary signals during a number of bit time intervals equal to the number of reading heads plus the nmnber of bit time intervals necessary to accommodate a number capable of indicating the length of the magnetic scale emplayed in the system in terms of the smallest. unit, 6. g., mils. To this extent, if the lands and grooves are each one mil wide, 16 bit: time intervals are adequate for a scale approximately inches long. Thus, in the example shown, the circulating register 32 has 20 bit time intervals as shown graphically in Fig. 2. The circulating register 32 also produces a clock pulse signal, Cp, which signal constitutes a positive voltage excursion at the end of each of the bit time intervals, as represented by the waveform l lll, Fig. 2. These cloekpulse signals, Cp, are made available on lead 43 in the apparatus shown in Fig. l and are applied to each of the flip-flops Q1, Q2, Q3 and Q5 of the storage-shifting register 30 and to the bit counter 33.

The operation of the apparatus is divided into two phases; namely, the "serial shift" and neenmulator phases. These phases are controlled by the principal and complementary outputs of phase control iiip-ll0p Q! Which, in turn, is set and reset by signals generated by the bit counter 38. The serial shift phase is concurrent with the bit time intervals r,, i, r, and t, while the accumulator phase is con-current with the remainder of the cit time intervals r,-r,,. The pit control 'lipaiop Qp is set by a bit-4 signal and reset h hitfiill signal, both cl which are generated by the hi. control 3% in response to clocl; pulse signals C from the circulating register 32. The hit counter 38 is simply a counter which produces an information level signal during the I, hit time interval, designated as the bit lsignal, and a second information level signal during the 11,, bit time interval, designated as the bit2i) signal. The bit-4 and bit-2O signals have Waveforms 102 and Ill-1, as shown in Fig. 2. The bit-4 and bit20 signals are employed to set or reset. respectively, the phase control flip-flop Qp whereby the principal output signal. Qp, therefrom is at the information level during bit time intervals 2 -23,, inclusive, and 0 during the remaining time interval. The complementary output, 6, on the other hand, is at the information level during bit time intervals 214,, inclusive. Signals Qp and Up have waveforms 106 and 108, respectively, as shown in Fig. 2.

The storage shifting register 30 is adapted to sample the configuration of binary signals produced at the output of binary signal generators 26-29 during bit time interval t,,,. Subsequently, during the serial shift phase, these signals thus sampled are shifted serially out of the register through the storage llipfiop Q1. Also, at the termination of the serial shift phase, each of the storage flip-flops Q1Q4 are reset to O by the Qp signal. An apparatus for accomplishing the above may comprise or" gates 44, 45; 46, 47; 48, 49; and 50, 51 having outputs connected to the set and reset inputs, respectively, of flip-flops Q1, Q2, Q3 and Q4. In addition, register 30 may include and gates 52, 53; 54, 55; 56, 57; and 58, 59, the outputs of which are connected to the inputs of the or gates 44, 45; 46, 47; 48, 49 and 50, 51, respectively. The principal and complementary outputs of the flip-flops Q2, Q3 and Q4 are connected, respectively, to the inputs of the and gates 52, 53; 54, 55; and 56, 57. The principal and complementary outputs from the flipflop Q1, on the other hand, are connected, respectively, to the inputs of and gates 60, 61. A remaining input to each of the "and gates 52, 53', 54, 55; 56, 57; and 6t), 61 is connected to the complementary output of the phase control flip-flop, Qp, so that the signals stored in the Hipflops Ql-Q4 are serially shifted out through Q1 during the serial shift phase as determined by signal 6,0. The principal and complementary signals thus serially shifted out of the storage-shifting register 30 are designated as A and A, respectively, and the bits of signal A are referred to as the present configuration of binary signals.

During operation, each of the flip-flops Q1, Q2, Q3 and Q4 is set during bit intervals 1 so as to sample and store the binary signal presently being generated by the binary signal generators 29, 23, 27 and 26, respectively. This is accomplished by applying, respectively, the output of each of the binary signal generators 29, 28, 27, 26 together with the bit signal to the inputs of and gates 62, 63, 64 and 65, the outputs of which are connected through or gates 44, 46, 48 and 50 to the respective set inputs of flip-flops Q1, Q2, Q3 and Q4. After the serial shift phase and at the commencement of the accumulator phase, the flip-flops Q1, Q2, Q3 and Q! are rest to zero by the application of the Qp signal from the phase control flip-flop Qp through the "or gates 45, 47, 49 and 51 to the rest inputs thereof, respectively.

The signals A and A thus serially shifted out of the storageshifting register are applied through "or gates 70, 72 to the set and reset inputs of the write flip-hop Qw of the circulating register 32 to store the signals A and A in the space on the drum corresponding to hit intervals r 11, t, and 1,. Simultaneously with the storing of the Signals A and A in the circulating register 32, the principal and complementary signals corresponding to the previous or last configuration of binary signals stored during the previous serial shift phase in the space on the drum allocated to hit intervals t,, I I, and t, is read by the read flip-flop Qr. The principal and complementary signals thus read from the drum are designated as B and 1 3 respectively.

The binary signals A, K, B, are then applied to the gating matrix which, in accordance with the present invention, is adapted to compare the corresponding bits of the present and last configurations of binary signals derived from the binary signal generators 26-29. As previously specified, the number of disagreements" resulting from such comparison is equal to the number of positions that the position along the scale 10 corresponding to the present configuration is away from that corresponding to the last configuration. It is evident that whenever the signals A and E or the signals A and B are at the information level, there is such a disagreement between the corresponding bits of the present and last configurations. Thus, gating matrix 40 may comprise a first and gate responsive to the signals A and B and second ant gate responsive to the signals A and B. The outputs from these first and second and gates are applied to an or gate, the output from which constitutes the output from the gating matrix 40. In order to count the number of disagreements, it is desirable to produce a pulse for each such disagreement during the serial shifting phase. This is accomplished by applying the complementary phase control signal Qp from the complementary output of the phase control flip-flop Qp together with the clock pulse signal Cp from the circulating register 32 and the output from the gating matrix 40 to an "and gate 74 whereby a clock pulse appears at its output for every disagreement during the serial shift phase. The output from the and" gate 74 is applied to the counting device 34 which device is adapted to count the total number of disagreements during any one serial shift phase interval. in the present case where only four reading heads 17-20 are employed, it is only necessary that the counting device 34 have three stages, i. e., the counting device 34 should be capable of recording a twodigit binary number.

During the accumulator phase of operation, it is desired to add or subtract the numbers of counts recorded by the counting device 34 to the number previously stored in the space corresponding to bit intervals ts-tzo in the circulating register 32. The principal and complementary signals read from the circulating register 32 by the read flip-flop Qr during the accumulator phase of operation is still designated as B and B. The signals B and B, however, now, represent the sum or ditlcrence previously recorded in positions on the drum corresponding to the bit intervals ls-lzo. This sum or difference will normally represent the total movement of the magnetic element 12 along the magnetic scale 10. In order to accomplish this addition or subtraction during the accumulator phase, the Qp signal from the pulse phase control tlip-tlop Op together with the clock pulses from the circulating register 32 are applied to an "and" gate 76, the output from which is, in turn, applied to the flip-flops C1 and C2 of the counting device 34 to serially shift any number stored therein out at the commencement of the accumulator phase of operation. The principal and complementary signals thus shifted out of the counting device 34 are designated as R0 and K0, respectively. The principal and complementary signals B and 15 from the circulating register 32 and the signals R0 and R0 from the counter 34 are applied to the full adder-subtracter 36 to produce a resulting sum or difference. The principal and complementary signals representing this sum or difference are designated as S0 and S0, respectively. The signals S0 and 30, respectively, are applied to and gates 78 and 80 along with the signal Qp provided by the phase control flip-flop Q0. The outputs from the and" gates 78 and 80 are then applied through the or gates 70, 72, respectively, to the set and reset inputs of the Write flip-flop Qw, thereby to record and store the signals S0 and So.

It is necessary to provide an instruction to the full adder-subtracter 36 so that the number represented by the signal R0 may be properly added or subtracted from the number represented by the signal B during the accumulator phase in accordance with direction of movement of the magnetic head 12 along the scale It). This instruction is provided in the form of the principal and complementaary outputs of the direction sensing flip-flop Cd, the state of which is determined during the serial shift phase of operation in a manner hereinafter explained. The bit20 signal is applied to the reset input of the direction sensing flip-flop Cd so that its principal output corresponds to zero level at the commencement of the serial shift phase of operation. When the principal output of the flip-flop Cd is at the zero level, the full addersubtracter 36 is instructed to add the number represented by signal R0 to the number represented by signal B. Alternatively, when the principal output of the flip-flop Cd is at the information level, the full adder-subtracter 36 is instructed to subtract the number represented by signal R0 from the number represented by signal B.

In formulating the aforementioned instructions to the full adder-subtracter 36, the principal output from the storage flip-flop Q4 of the storage-shifting register 30 is employed as a control bit to determine the ultimate state of the direction-sensing flip-flop Cd. In that this control bit is the last to be shifted from the register 30, the storage flip-flop Q4 may be employed directly to store it and to record subsequent changes. However, it is obviously within the teachings and scope of the present invention to use an additional flip-flop, in which case any one of the bits of a sample configuration may be employed as the control bit.

In the present case, the individual bits of the present and last configurations are subtracted from each other in a direction determined by the control bit whereby the production of one or more carries is indicative of a movement in the negative direction and the production of zero carries is indicative of either a zero or positive movement. The afore-mentioned differences are taken in accordance with the following rules for each pair of corresponding bits of the last and present configurations. When the control bit is one, i. e., when the principal output of the storage flip-flop Q4 is at the information level, the bit of the last configuration is subtracted from that of the present configuration. On the other hand, when the control bit is zero, i. e., when the complementary output of the storage fiip fiop Q4 is at the information level, the bit of the present configuration is subtracted from that of the last configuration. In addition to the above, when the two bits of the present and last configurations being compared are l, the control bit is made to be 0. Further, when the two bits of the present and last configurations are 0, the control bit is made to be 1. The carry signals referred to above are generated by applying the principal and complementary signals Q4, Q4, A, A and B, B to gating matrix 42. The gating matrix 42 may include, for example. a first "and gate responsive to the signals Q4, A and B and a second and gate responsive to the signals Q4, A and B. The outputs from these first and second and" gates are then applied to an from which constitutes the output of the matrix 42. As it is desired to generate carries only during the serialshift phase, the output from the matrix 42 is applied together with the serial shift phase signal Qp to an and gate 82, the output from which is connected to the set input of the direction sensing flip-flop Cd.

In accordance with the convention employed, a control bit of 1 corresponds to the principal output of the storage flip-flop Q4 being at the information level. As previously indicated, it the two bits being compared are l, it is desired that the control bit be made 0. Also, if the two bits being compared are 0, it is desired that the control bit he made 1. These changes are of course, only made during the serial-shift phase of operation. The above function: may be accomplished by applying the binary signals A, B and Qp to the and" gate 58, the output of which is applied through the or" gate 50 to the set input of the storage flip-flop Q4. In addition, the binary signals A. B and Qp are applied to the inputs of the and gate 59, the output of which is applied through the or gate 51 to the reset input of the storage flip-flop Q4.

In order to illustrate the truth of the aforementioned logic incorporated in the described embodiment of the present invention. the following Tables lI-lX are presented which cover all possible combinations for the present case wherein the four leading heads l720 are employed. In each of the following Tables II-IX, a particular last configuration of binary signals for one of the eight positions of a complete cycle along the scale 10 appears in the left column as illustrated. The particular position is identified by the lower case letter employed to identify the corresponding position in Table I. In each of the Tables lI-IX, the seven possible present configurations appear in the columns to the right and are or" gate, the output till identified by the proper lower case letter as per Table I with the number of positions away from the last configuration indicated in parenthesis. In this respect, a movement to the left is regarded as negative and a movement to the right as positive.

The direction of the aforementioned subtraction as would be instructed by the action bit is then, in each case, indicated by an arrow. An arrow pointing to the right indicates that the bit of the last configuration is to be subtracted from the corresponding bit of the present configuration whereas an arrow pointing to the left indicates that the bit of the present configuration is to be subtracted from the bit of the last configuration.

Further, below each column of present configurations, there appears a number labeled Counts" which is the number of disagreements between the bits of the present and last configurations. As previously explained, the counts are representative of the distance moved between samplings. The speed along the scale 10 is controlled so that a present configuration is never more than 3 counts or positions away from the position corresponding to the last configuration.

In the next column below Counts there appears a horizontal column labeled Carries which is the number of carries generated when the suhstractions are taken in the directions indicated by the arrows. The generation of one or more carries indicates tlut the displacement has been in a negative direction whereas no carries indicates that the displacement has either been zero or in a positive direction. Thus, in the horizontal column labeled Direction," directions to the right or left in accordance with the carries generated is indicated by plus or minus signs, respectively.

TABLE Last Configu- Present Configurations ration l l f fi gH- l H- t(+3) 1 1 1 im- 04- (n- 0(- 1 1 a 1 l1 th m- Ut 0 l 1 i A 1 u mu t] 1 1 1 1 a 0+ 3 2 l U v l 2 3 2 l 1 u u u 0 Direct.) -i- -5- W WWWWJ .Wc. i iifici, c v,

TABLE lll Last Configu- Present Configurations ration 4" ,]l wi Mi-U ii- J'(+ 1 1% 0(- 0( 0 0e- 1 1 1(- l 0 0(- 0(- 1 1 1 1 0 0% De- 0 1 1 1 1 0(- 0e- 3 2 1 (J 1 2 3 1 2 1 0 0 0 0 Direction TABLE IV Last Oonfigu- Present Configurations ration f(- G( M (+1) j(+ l Oel1t- 0 0(- 1 1 1e 0 0e O 0 1 1e 1(- G 0(- 0( 0( 1 1 1 0 0 t) 2 1 1 2 3 2 1 D 0 0 0 Direction TABLE V Following is an example of the derivation of some of the figures in the Table II, above:

Last Conflgu- Present Configurations ation Configurations Control Bit Counts I t P t (Dls- Difrec'tgon C 1 id) j(+1) k +2) [(+3) JilS resen agree- 0 Su arr-0s ments) Initial Final traction D 1 1 1 f r. e(-1) ot- 0 1 1 0+- 0 0e 1 mo m- 0(- 0 1 1 1 1 1 0 1 2 3 1 1 0 1 (1 o 0 0 o u 1 1 0 0 0 a 0 Direction 1 .s 1 D 0 0 0 Total 1 Total 1 TABLE VI As can be seen, there is one disagreement or count, indicating a movement of one position, and one carry L to a 0 indicating that the movement was in a negative direction.

asmtpoiji1 gu- Present onfignrations (hat is claimgd is:

1. A direction sensing and detection apparatus adapted 1( 11 m1) 1(+1) [(+2) m(+3) to operate in response to binary signals derived from N 1 reading heads wherein N is an integer equal to or greater 0%. [1 1 a, 1 1 1 than two, said N reading heads being disposed along a 1 1 1 linear scale at successive intervals equal to WIN, wherein 0 0+- o 0 1 1 20 De- 0a 1 71 is the distance of one complete cycle along the scale, f 1 8 3 said direction sensing and detection apparatus comprising Direction a first register for storing samples of a last configuration of the binary signals from said N reading heads, means including a second register for sampling and storing samples of a present configuration of binary signals from TABLE V11 said N reading heads, means tor effecting said sampling at sufliciently short periodic intervals of time to main: said resent configurations always corresoond to a oo p p Last Cpnfigw Present Configurations SltlOn 110 more than (N-l) positlons away from that m of said last configuration, and means for determining and h 3 1 I 2 k I i counting the number of disagreements in the levels of l( (0) (+1) lm(+2) "(+3) the corresponding bits of said samples of said last and new 0( G 11 1 1 1 0 configurations of signals, the number of said disagreements 11g 11 I; a b, 1 I; 1 3 1 :1 1 3 being equal to the number of positions along said scale 1 1P 1 1 that the position corresponding to said present configura- 1e (l o u\ 0 1e 1 3 2 1 11 1 2 3 tron of signals is away from the position corresponding 1 2 l l! O U 0 nu 0 r Direction H to said last confi ration of si nals 1 L 2. The direction sensing and detection appercrus as defined in claim 1 including a bistable device, means for subtracting or adding said number of disagreements to Y a prior sum in accordance with the state of said bistable TABLE VIII device, means for generating carry signals from the differences between corresponding individual bits or" said Lastconfigw Present Configurations last and present configurations of signals to control the ration state of said bistable dev1ce, the directlon of each of said differences being initially determined by a predetermined Z :(-3) (2) lit-1) 1(0) m(+1) n(+2) o(+3) one of the bits of said present configuration, and means for subsequently altering the direction of said differences 1 1 1 1 0 ne in response to a signal derived from a comparison of the 1:3: 11 j 0 1 I; 1 j i I, respective bits of said last and present configurations of ((lj. 3e 0e o 1 1 13 gi h 2 i 8 a 0 11 3. A direction sensing and detection apparatus adapted Dirvfiikm-- H 1 1 ito operate in response to binary signals derived from N k e d M iv reading heads wherein N is an integer eq al to or greater than two, said N reading heads being disposed along a linear scale at successive intervals equal to M'ZN, heroin TABLE EX A is the distance of one complete cycle along the sca e, 1 1w inf said direction sensing and detection apparatus cornpri ing a first register for storing samples of a last configure" Last Configtb Prose 1 toxifigu 1 r 1 1 1 ration tion of the binary signals from said N reading heads,

Awwm ddi ma ns 1. means including a second register for sampling and storm -51; j 1 1 "W21 ing samples of a present configuration of binary signals --l t" from said N reading heads, means for effecting said i 1 1 F 1 "t 1 11% he he sampling at sufiiciently short periodic intervals of time ti ]-+1e1- 1-t0- u w 1 n i} n i I 1 1 1 1 U to make said lust and present configurations alwap cor l u J u 1 1 1 1 1 respond to positions no more than (N-l) positions apart, 3 5 i 8 l g a means for simultaneously serially shifting said last and Direction 1- present configurations of binary signals from said first and second storage registers, respectively, said first storage register providing first and second binary signals and said second storage register providing third and fourth binary signals, said second and fourth binary signals being complementary to said first and third binary signals, respectively, a first "and gate responsive to said first and fourth binary signals, a second and gate responsive to said second and third binary signals, an or gate responsive to the output signals from said first and second and" gates, and a counter circuit responsive to the output from said "or" gate, the number recorded in said counter after said last and present configurations of binary signals have been completely shifted out of said first and second registers being equal to the number of positions along said scale between the positions corresponding to said last and present configurations of signals.

4. The direction sensing and displacement detection apparatus as defined in claim 3 wherein said first register includes N flip-flops for storing the N bits of said present configuration of binary signals, the Nth fiipdlop initially storing the last bit of said present configuration to be shifted from said first register, means coupled to said Nth flip-flop for providing 5th and 6th binary signals representative of the states of the said Nth flip-flop, said 6th binary signal being complementary to said 5th binary signal, a third and gate responsive to said second and fourth binary signals for producing an output signal adapted to set said Nth flip-flop, a fourth and gate responsive to said first and third binary signals for pro ducing an output signal adapted to reset said Nth fliptlop, a fifth and" gate responsive to said first, fourth and fifth binary signals, a sixth and gate responsive to said second. third and sixth binary signals, an or gate re sponsive to the output signals from said fifth and sixth "and gates for generating a carry signal, and means re sponsive to said carry signal for producing a direction sensing signal indicative of the direction of movement from the position corresponding to said last configuration to the position corresponding to said present configuration.

5. The direction sensing and displacement detection apparatus as defined in claim 4 which additionally includes an accumulator, means for serially shifting the number stored by said counter out of said counter into said accumulator subsequent to said last and present configurations being completely shifted out of said first and second registers, respectively, and means responsive to said direction sensing signal for controlling whether to add or subtract the number being shifted out of said counter from the number initially stored in said accumulator whereby the resulting number therein is changed by an amount representative of the net movement of said reading heads along said scale.

6. A direction sensing and displacement detection apparatus for operating in response to binary signals derived from N reading heads adapted to read a linear scale wherein N is a positive integer equal to or greater than two, said N reading heads being disposed at successive intervals of )t/ZN along said scale, 7\ being the distance of one complete cycle therealong, said direction sensing and displacement detection apparatus comprising a first storage register including at least N flip-flops; a circulating register for providing a circulating storage facility for a predetermined number greater than N bit time intervals and for producing a clock-pulse signal at the end of each of said bit time intervals; a bit counter responsive to said clock-pulse signals for producing a bit-N pulse signal during the Nth bit time interval and for producing a bit-total pulsc signal during the last bit time interval; means responsive to said bit-total pulse signal for sampling and storing the present configuration of the binary signals derived from said N reading heads in the N respective flip-flops of said first register; a phase control flip-flop responsive to said bit-N and bit-total pulse signals for producing a phase control signal having a first portion and a remaining portion, said first portion being concurrent with the first N bit time intervals and said remaining portion being concurrent with the remaining bit time intervals; means responsive to said phase control signal for serially shifting the present configuration of binary signals out of said first register and into the first N bit time positions of said circulating register wherein said configuration is designated as the last configuration; means responsive to said phase control signal for serially shifting said present and last configurations of binary signals from said first and circulating registers, respectively, during the next succeeding first N bit time intervals, said first register providing first and second binary signals and said circulating register providing third and fourth binary signals, said second and fourth binary signals being complementary to said first and third binary signals, respectively; a first and gate responsive to said first and fourth binary signals; a second and gate responsive to said second and third binary signals; an or gate responsive to the output signals from said first and second and gates; and a counting device coupled to the output of said or gate whereby the number in said counter at the commencement of said remaining bit time intervals is equal to the number of positions between the positions corresponding to the present and last configurations of binary signals.

References Cited in the file of this patent UNITED STATES PATENTS 2,462,292 Snyder Feb. 22, 1949 2,604,004 Root July 22, 1952 2,628,539 de Neergaard Feb. 17, 1953 2,672,393 Cooper Mar. 16, 1954 2,784,911 Cooper Mar. 12, 1957 

